Single-slope ramp analog-to-digital converters (SSR-ADC) are used in ICs for converting analog signals into digital. A simple SSR-ADC architecture 100 is shown in FIG. 1. A ramp generator 120 generates a sloping voltage level between two input voltages, Vlow and Vhigh. The ramp generator 120 is coupled to a comparator 140, which compares an analog input signal Vin, to be digitized, to the ramped input voltage from the ramp generator. An n-bit counter 160 (in this example, a 3 bit counter) is coupled to a latch 180. The latch 180 is responsive to a change in the output of the comparator 140 to latch a current value of a count from the counter 160. A timing diagram illustrates the operation in FIG. 2. In this example, the ramp signal is increased between 1 and 2 volts, while the analog input voltage Vin is set to 1.7 volt. The counter 160 starts counting in sync with the start of the ramp signal's increase in voltage. The latch 180 is transparent and “passes” counter digital bits to the data output as long as the ramp signal is below the analog input voltage Vin. Once the ramp voltage exceeds the input voltage, the comparator output voltage switches causing the latch to hold the last counter word, which represents the analog signal Vin in digital form.
One problem with SSR-ADCs is the analog-to-digital conversion speed. To convert an analog signal into a digital n-bit word, SSR-ADC requires 2n times the master clock cycle. For example, a 10-bit representation of an analog signal can be converted into digital form after 1024 clock cycles. SSR-ADC is considered slow when compared with other ADC topologies, such as Flash ADC, which requires only 1 clock cycle for conversion, or Successive Approximation Register (SAR) ADC, which requires n-clock cycles for conversion.
SSR-ADC, however, is very suitable for column-parallel integration in image sensors, such as CMOS image sensors. One such image sensor is shown in FIG. 3. A pixel array 300 outputs row data onto shared column lines as controlled by a row decoder 320. Each column's pixel signal is read by an analog signal processor (ASP) 340, which passes the processed data to a plurality of ADCs 360. The ADCs 360 scanned by column decoder 380 sequentially output the data to a column bus 381, which is connected to a digital signal processor (DSP) 390. The DSP 390 processes and outputs the data in digital form. Column parallel architectures have m-number of ADCs integrated together, working in parallel to convert m-number of analog signals at the same time.
FIG. 4 shows the structure of the SSR-ADCs 360 integrated in CMOS image sensor columns. As can be seen, only one ramp generator 400 is used to provide a ramp signal to multiple comparators 420 coupled in parallel. A global counter 440 is coupled to m, n-bit transparent digital latches 460. Although the SSR-ADC operates at a much slower speed than SAR-ADC or Flash ADC, it requires much less power and requires smaller integrated circuit (IC) area. Nonetheless, it is desirable to increase the speed of ADCs used in image sensors, while maintaining the benefits of SSR-ADCs.